A non-volatile memory, such as Flash memory, retains stored data even if power to the memory is removed. A non-volatile memory cell stores data, for example, by storing, electrical charge in an electrically isolated memory gate or in a charge-trapping layer underlying a control gate of a field-effect transistor (FET). The stored electrical charge controls the threshold of the FET, thereby controlling the memory state of the cell.
A split-gate memory cell is a type of non-volatile memory cell, in which a select gate is placed adjacent a memory gate. During programming of a split-gate memory cell, the select gate is biased at a relatively low voltage, and only the memory gate is biased at the high voltage to provide the vertical electric field necessary for hot-carrier injection. Since acceleration of the carriers takes place in the channel region mostly under the select gate, the relatively low voltage on the select gate results in more efficient carrier acceleration in the horizontal direction compared to a conventional Flash memory cell. That makes hot-carrier injection more efficient with lower current and lower power consumption during programming operation. A split-gate memory cell may be programmed using techniques other than hot-carrier injection, and depending on the technique, any advantage over the conventional Flash memory cell during programming operation may vary.
In the manufacture of the split-gate memory cell, the oxide-nitride (ON) spacer isolating between the memory gate and select gate may be easily and seriously damaged by common etching processes. This damage issue may influence the breakdown voltage between the memory gate and the select gate, which in turn impacts the overall electrical performance. Accordingly, there is a need for a memory device and methods for preventing the ON spacer damage in the manufacturing process thereof in order to maintain the performance and reliability of the memory device.
In an actual case, refer to FIG. 9, during the common etching process, the oxide-nitride (ON) spacer isolating between the memory gate and the select gate is apt to be damaged by phosphoric acid (H3PO4) solvent, especially during silicon nitride (SiN) removal process, It will cause a high leakage current between the memory gate and the select gate and lower the breakdown voltage between the memory gate and the select gate, thereby impact the performance and reliability of the memory device.
Currently, in view of preventing the over etching upon the spacer, a method of fabricating a memory structure by forming an oxide on top of a SiN spacer is provided.
There is a need for a memory device and methods for preventing the ON spacer damage in the manufacturing process thereof in order to maintain the performance and reliability of the memory device.